1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a vertical transistor and a method for fabricating the same, to improve operation reliability of the transistor and to realize minuteness in the semiconductor device.
2. Discussion of the Related Art
With high integration of a semiconductor device, a size of the semiconductor device decreases, whereby a channel length of the semiconductor device also decreases. According to the decrease of the channel length in the semiconductor device, there may be the undesirable electric characteristics, for example, a short channel effect.
In order to overcome the short channel effect, it is necessary to realize the vertical decrease such as the decrease in thickness of a gate insulating layer and a junction depth of source/drain as well as the horizontal decrease such as the decrease in length of a gate electrode. Also, according to the horizontal and vertical decrease, a voltage of applying power lowers, and a doping density of a semiconductor substrate increases. Especially, there is demand for effective control of the doping profile of a channel region.
However, on the decrease in size of the semiconductor device, an operation power for electronic equipment is not low. For example, in case of an NMOS transistor, injected electrons of the source are excessively accelerated in state of a high potential gradient, so that hot carriers generate. Accordingly, an LDD (Lightly Doped Drain) structure having an improved NMOS transistor has been researched and developed.
In the LDD-structure transistor, a lightly doped n-type (n−) region is positioned between a channel and a highly doped n-type (n+) source/drain, and the lightly doped n-type (n−) region buffers a high drain voltage around the drain junction, so that it is possible to prevent inducement of the rapid potential gradient, thereby preventing the generation of hot carriers. On research for the technology of the high-integration semiconductor device, various methods for fabricating an MOSFET of the LDD structure have been proposed. Among them, the method for forming the LDD structure by forming spacers at sidewalls of the gate electrode is most generally used.
However, according to the high integration in the semiconductor device, it is impossible to perfectly control the short channel effect with the LDD structure. To satisfy this request for the optimal structure of minimizing the short channel effect, a vertical transistor is proposed, which is suitable for realizing minuteness in the semiconductor device by decreasing the channel length.
In the vertical transistor, the channel region is formed in vertical, whereby the channel length is determined dependent on not a width of an active region but a thickness of the active region. As compared with a conventional plane-type transistor, the vertical transistor has the advantageous characteristics such as the decrease of the channel length without photolithography.
However, the related art vertical transistor has the following disadvantages. In the related art vertical transistor, the channel is formed in vertical, whereby it has difficulties in uniformly implanting impurity ions to form impurity ions areas, and in minimizing the short channel effect. As a result, the related art vertical transistor may have the misoperation.